There is a constant drive within the semiconductor industry to increase the operating speed of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for computers and electronic devices that operate at increasingly greater speeds. This demand for increased speed has resulted in a continual reduction in the size of various features of the integrated circuit devices, e.g., transistors, word lines, etc. For example, all other things being equal, the smaller the channel length of the transistor, the faster the transistor will operate. Thus, there is a constant drive to reduce the size, or scale, of the features of a typical memory device to increase the overall speed and capabilities of the memory device, as well as the speed and capabilities of electronic devices incorporating such memory devices.
A variety of semiconductor memory devices are used extensively in many consumer products. Illustrative examples of such memory devices include dynamic random access memory (DRAM) and flash memory devices. FIG. 1 depicts an illustrative layout of a schematically depicted DRAM memory device 10 comprised of a semiconducting substrate 19. In general, the memory device 10 is comprised of a memory array 11 and a plurality of peripheral circuits 12. By way of example only, a plurality of schematically depicted illustrative peripheral circuits 12 are depicted in FIG. 1. More specifically, the illustrative peripheral circuits 12 comprise read-write circuits 12A, sense amp circuits 12B and power management circuits 12C. The illustrative peripheral circuits depicted in FIG. 1 are not exhaustive of all such peripheral circuits 12 on the memory device 10. In other words, the peripheral circuit 12 may comprise any circuitry on the memory device 10 other than the circuitry found within the memory array 11.
The memory array 11 includes a multitude of memory cells arranged in rows and columns. Each of the memory cells is structured for storing digital information in the form of a logical high (i.e., a “1”) or a logical low (i.e., a “0”). To write (i.e., store) a bit into a memory cell, a binary address having portions identifying the cell's row (the “row address”) and column (the “column address”) is provided to addressing circuitry in the memory device 10 to activate the cell, and the bit is then supplied to the cell. Similarly, to read (i.e., retrieve) a bit from a memory cell, the cell is again activated using the cell's memory address and the bit is then output from the cell.
FIG. 2 is a cross-sectional view of the line 1-1 in FIG. 1 showing a portion of the illustrative memory device 10. Depicted therein is an illustrative transistor 15, which is a portion of a peripheral circuit 12A, and a plurality of word lines 111 within the memory array 11. Typically, the memory array 11 is much more densely packed than the peripheral circuits 12A, i.e., the pitch between adjacent word lines 111 within the memory array 11 is typically much tighter than that in the peripheral circuits 12. For example, the spacing 112 between adjacent word lines 111 in the memory array 11 may be approximately 50 to 90 nm, whereas the spacing between adjacent transistors 15 in the peripheral circuits 12A may be on the order of approximately 240 to 600 nm.
As indicated in FIG. 2, the illustrative transistor 15 comprises a gate insulation layer 151, a gate electrode 152, a metal layer 153 and a cap layer 154 comprised of, for example, silicon nitride. The transistor 15 further comprises a plurality of source/drain regions 13 and a sidewall spacer 14. The word lines 111 within the memory array 11 also include a similar structure. The feature size W of the word lines 111 may be on the order of approximately 50 to 90 nm. Typically, the spacing 112 between adjacent word lines 111 in the array 11 is approximately equal to the feature size W of the word line 111. A sidewall spacer 113 is also formed adjacent to the word lines 111 depicted in FIG. 2. Lastly, isolation regions 114 are formed in the substrate 19 as is well known in the art.
Typically, the sidewall spacers 14 on the peripheral circuits 12A, as well as the sidewall spacers 113 formed in the memory array 11, are formed at the same time and from the same layer of material. Thus, the thickness D1 of the spacers 14 formed in the peripheral circuits 12A is approximately the same as the thickness D2 of the spacers 113 formed within the memory array 11. Due to the densely packed nature of the word lines 111 in the memory array 11, the thickness D2 of the spacers 113 is limited by the size of a spacer 113 that may be reliably formed in the very small spacing 112 between adjacent word lines 111. This is problematic in that, for a variety of reasons, it may be desirable to make the spacer 14 on the peripheral circuits 12A thicker than the spacer 113 within the memory array 11. For example, formation of the source/drain regions 13 of the transistors 15 in the peripheral circuits 12A generally involves an initial lightly doped drain (LDD) implant, followed by the formation of spacers 14 and then followed by a source/drain implant step. However, since the spacer 14 and the spacer 113 are typically formed by the same process, the thickness D1 is similar to the thickness D2. Thus, the thickness D1 of the spacer 14 is constrained by the spacing 112 between the word lines 111 in the memory array 11, and the source/drain regions 13 on the peripheral circuits 12A may not be located as precisely or formed as deep as they would otherwise be if the formation of the spacers 14 was independent of the formation of the spacers 113. Even if the spacers 14 could be formed independent of the formation of the spacers 113, the process of forming the spacers 14 and 113 separately would require an additional photolithographic process that would increase manufacturing cost.
The present invention is directed to various methods that may solve, or at least reduce, some or all of the aforementioned problems.